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DATA SHEET
MOS INTEGRATED CIRCUIT
PD16664
144/160/184/208-OUTPUT LCD COLUMN (SEGMENT) DRIVER WITH RAM
DESCRIPTION
The PD16664 is a column (segment) driver with internal RAM and can drive a full-dot LCD. Equipped with 144/160/184/208-output pins and a display RAM of 208 x 160 x 2 bits, this driver can display any of four gray levels selected from a 25-level palette. By using this IC in combination with the PD16667, 144 x 128 pixels to 416 x 320 pixels can be displayed.
FEATURES
* Internal display RAM : 208 x 160 x 2 bits * Logic voltage * Duty * Number of outputs * Display : 2.4 to 3.6 V : 1/128, 1/160 selectable : 144,160,184 and 208 pins selectable : Four gray levels (selectable from 25-level palette)
* Memory management : Packed pixel method * Supports 8/16-bit data bus
ORDERING INFORMATION
Part number Package TCP (TAB) 2/4-side Standard TCP
PD16664N-xxx PD16664N-001
Remark
The TCP's external shape is customized. To order the required shape, please contact an NEC salesperson.
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local NEC representative for availability and additional information.
Document No. S13780EJ1V0DS00(1st edition) Date Published September 1999 NS CP(K) Printed in Japan
The mark * shows major revised points.
(c)
1998, 1999
PD16664
1. PIN NAME
Pin NameNote D0-D15 A0-A16 /CS VCC2 /OE /WE /UBE RDY Control signals PL0 PL1 DIR DMODE CMODE0,1 MS VCC2 BMODE /REFRH TEST /RESET /DOFF OSC1 OSC2 STB /FRM VCC1 PULSE L1 L2 /DOUT Liquid crystal drive Power Y1-Y208 GND VCC1 VCC2 V0 V1 V2
Classification CPU interface
I/O I/O I I I I I O I I I I I I I I/O I I I - - I/O I/O I/O I/O I/O O O - - - - - - Data bus: 16 bits Address bus: 17 bits Chip select Read signal Write signal Upper byte enable
Function
Ready signal to CPU ("H": ready) Specifies LSI layout position (No. 0 to 3) Specifies LSI layout position (No. 0 to 3) Specifies liquid crystal panel layout position Duty selection ("H" = 1/128 duty, "L" =1/160 duty) Number of column outputs selection Master/slave selection ("H": master mode) Data bus bit selection ("H" = 8 bits, "L" = 16 bits) Self-diagnosis reset pin (wired-OR connection) Test pin ("H" = test mode, with pull-down resistor) Reset signal Display OFF input signal External resistor pin for oscillator External resistor pin for oscillator Column drive signal (MS pin "H" = output, MS pin "L" = input) Frame signal (MS pin "H" = output, MS pin "L" = input) 25-level pulse modulation clock Row driver drive level select signal (first line) Row driver drive level select signal (second line) Display OFF output signal Liquid crystal drive output Ground (two pins for VCC1 system, three pins for VCC2 system) Power supply for liquid crystal drive and row driver interface Power supply for logic Liquid crystal drive analog power Liquid crystal drive analog power Liquid crystal drive analog power
Note VCC2 system pins : D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, BMODE, PL0, PL1, DIR, OSC1, OSC2, /RESET, /DOFF, TEST, MS, CMODE0, CMODE1, DMODE VCC1 system pins : STB, /FRM, L1, L2, /DOUT, PULSE Remark /xxx indicates active low signals.
2
Data Sheet S13780EJ1V0DS00
PD16664
2. BLOCK DIAGRAM
CMODE0,1 DIR PL0, 1 TEST Address input control Address management circuit Arbiter RAM 208 x 160 x 2 bits
A0-A16 Control /CS, /OE /WE, /UBE RDY BMODE D0-D15
Data bus control
/REFRH /RESET MS STOP OSC1 CR oscillator OSC2 /DOFF DMODE Liquid crystal timing generation VCC2 operation PULSE /FRM STB Self-diagnosis circuit Level shifter VCC1 operation
Data latch (1)
Gray level generation circuit
Data latch (2)
Internal timing generation Gray level control
VCC2 operation
VCC1 operation DEC
Liquid crystal drive circuit 208 outputs
V0 V1 V2
PULSE
/FRM
STB /DOUT L1
L2
Y1 Y2 Y3
Y208
Data Sheet S13780EJ1V0DS00
3
PD16664
3. BLOCK FUNCTION
(1) Address management circuit This circuit converts addresses from the system via A0 to A16 into addresses corresponding to the memory map of the internal RAM. By using this function and four PD16664 modules, addresses for up to 416 x 320 pixels can be managed, making it easy to construct a liquid crystal display system. Addresses 1FF00H to 1FF1EH are allocated to a gray level palette register, and any four gray levels can be selected from a 25-level palette. (2) Arbiter This circuit arbitrates conflicts between access by the system to the RAM and reading the RAM by the LCD driver. (3) RAM This is a static RAM of 208 x 160 x 2 bits (single port). (4) Data bus control This circuit controls the data transfer direction depending on whether the system reads or writes the RAM of the
PD16664.
The data bus width can be changed between 8 and 16 bits by the BMODE pin. (5) Gray level generation circuit This circuit offers 25 levels by means of frame interpolation and pulse width modulation. (6) Internal timing generation This circuit generates internal timing signals for each block from the /FRM and STB signals. (7) CR oscillator This oscillator generates a clock that serves as the reference of the frame frequency in the master mode. Because this CR oscillator has an on-chip capacitor, the necessary oscillation frequency can be adjusted by using an external resistor. Oscillation is stopped in the slave mode. (a) 1/160 duty The frame frequency is 1/1296 of the oscillation frequency of this oscillator. For example, when the frame frequency is 70 Hz, the oscillation frequency is 90.72 kHz. (b) 1/128 duty The frame frequency is 1/1040 of the oscillation frequency of this oscillator. For example, when the frame frequency is 70 Hz, the oscillation frequency is 72.80 kHz. (8) Liquid crystal timing generation This circuit generates the /FRM (frame signal), STB(column drive signal strobe), and PULSE (25-level pulse modulation clock) signals in the master mode. 4
Data Sheet S13780EJ1V0DS00
PD16664
(9) Gray level control This circuit implements the 4-gray level display. (10) Data latch (1) This circuit reads data for 208 pixels from RAM and latches it. (11) Data latch (2) This circuit latches data for 208 pixels in synchronization with the STB signal. (12) Level shifter The level shifter converts the operating voltage of the internal circuit(VCC2) into the voltage for the liquid crystal driver circuit and row driver interface (VCC1). (13) DEC This is a decoder that decodes gray level display data to liquid crystal drive voltages V0, V1, or V2. (14) Liquid crystal drive circuit This circuit selects liquid crystal drive voltage V0, V1, or V2 corresponding to gray level display data and the display OFF signal (/DOFF), to generate a liquid crystal application voltage. (15) Self-diagnosis circuit If the operation timing of the master chip and that of the slave chip differ due to external noise, this circuit automatically detects the difference and generates a refresh signal to all column drivers.
Data Sheet S13780EJ1V0DS00
5
PD16664
Address Map Image (CMODE0 = L, CMODE1 = L, DMODE = L)
A7 through A0 specify column direction. Y1 Y208 L1 Address incrementing direction A16 through A8 specify line direction. L160 L1 Address incrementing direction L160 Y208 No. 1 Y1 Y208 No. 3 Y1 No. 0 No. 2 Y1 Y208
6
Data Sheet S13780EJ1V0DS00
PD16664
4. DATA BUS
The byte data ordering on the data bus is little endian, in common with most NEC and Intel buses.
4.1 16-bit Data Bus (BMODE = L)
Byte access
D0 to D7 00000H Address incrementing direction 00002H 00004H : :
D8 to D15 00001H 00003H 00005H : :
Word access
D0 to D7 00000H Address incrementing direction 00002H 00004H : :
D8 to D15
If the system accesses the PD16664 in word(16-bit) or byte(8-bit) units, /UBE (upper byte enable) and A0 specify whether bytes D0 to D7 or bytes D8 to D15 have valid data.
/CS
/OE
/WE
/UBE
A0
MODE D0 to D7
I/O D8 to D15 Hi-Z Dout Dout Hi-Z Din Din X Hi-Z Hi-Z
H L
X L
X H
X L L H
X L H L L H L X H
Not selected Read
Hi-Z Dout Hi-Z Dout
L
H
L
L L H
Write
Din X Din
L L
H X
H X
X H
Output Disable
Hi-Z Hi-Z
Remark
X : Don't care Hi-Z : High impedance
Data Sheet S13780EJ1V0DS00
7
PD16664
4.2 8-bit Data Bus (BMODE = H)
D0 to D7 00000H Address incrementing direction 00001H 00002H : :
/CS
/OE
/WE
MODE D0 to D7
I/O D8 to D15 Note Note Note Note
H L L L
X L H H
X H L H
Not selected Read Write Output disable
Hi-Z Dout Din Hi-Z
Note Leave D8 to D15 open because they are internally pulled down. Remark X: Don't care Hi-Z: High impedance
8
Data Sheet S13780EJ1V0DS00
PD16664
5. RELATION BETWEEN DATA BITS AND PIXELS
Because the PD16664 displays four gray levels, 1 pixel consists of 2 bits. The RAM consists of 4 pixels (8 pixels per word) using the packed pixel method. (1) BMODE = L Byte (8-bit) access
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14 D15 Pixel 8
Pixel 1
Pixel 2
Pixel 3 00000H
Pixel 4
Pixel 5
Pixel 6
Pixel 7 00001H
Liquid crystal panel
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00001H
00002H
00003H
Word (16-bit) access
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10 D11 Pixel 6
D12 D13 Pixel 7
D14 D15 Pixel 8
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
00000H
Liquid crystal panel
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00002H
(2) BMODE = H
D0
D1
D2
D3
D4
D5
D6
D7
D0
D1
D2
D3
D4
D5
D6
D7
Pixel 1
Pixel 2
Pixel 3
Pixel 4
Pixel 5
Pixel 6
Pixel 7
Pixel 8
00000H
00002H
Liquid crystal panel
Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8 Pixel 1 Pixel 2 Pixel 3 Pixel 4 Pixel 5 Pixel 6 Pixel 7 Pixel 8
00000H
00001H
00002H
00003H
Data Sheet S13780EJ1V0DS00
9
PD16664
6. GRAY LEVEL CONTROL
The gray level control of the PD16664 offers a 25-level palette by means of frame interpolation and pulse width modulation. From this palette, four gray levels are selected and registered in a gray level palette register.
7. GRAY LEVEL PALETTE REGISTER
The gray level palette register selects four gray levels from 25 levels in advance. This register is allocated to 1FF00H to 1FF1EH, and its relation with gray level data is as shown below. The gray level palette register can be set for each layout position of the column driver (No. 0 to 3) that is determined by PL0 and PL1.
Address
Layout Position No.
Gray Level Data (Display Data) Dn+1Note DnNote 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1FF00H 1FF02H 1FF04H 1FF06H 1FF08H 1FF0AH 1FF0CH 1FF0EH 1FF10H 1FF12H 1FF14H 1FF16H 1FF18H 1FF1AH 1FF1CH 1FF1EH No.3 No.2 No.1 No.0
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
Note n = 0, 2, 4, 6, 8, 10, 12, or 14
10
Data Sheet S13780EJ1V0DS00
PD16664
8. RELATION BETWEEN GRAY LEVELS AND GRAY LEVEL PALETTE DATA
The relation between the gray levels and the gray level palette data set by the gray level palette register is as follows:
PMODE D4 Gray level 0 Gray level 1 Gray level 2 Gray level 3 Gray level 4 Gray level 5 Gray level 6 Gray level 7 Gray level 8 Gray level 9 Gray level 10 Gray level 11 Gray level 12 Gray level 13 Gray level 14 Gray level 15 Gray level 16 Gray level 17 Gray level 18 Gray level 19 Gray level 20 Gray level 21 Gray level 22 Gray level 23 Gray level 24 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1
Gray Level Palette Data D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
Remark
OFF
1/3
2/3
ON
Data Sheet S13780EJ1V0DS00
11
PD16664
9. LSI LAYOUT AND ADDRESS MANAGEMENT
Addresses are managed so that up to four PD16664s can be used to organize a liquid crystal display of 416 x 320 pixels. Four modules can be connected on the same bus with the /CS, /WE, and /OE pins shared. The system can treats one screenful of the liquid crystal display as one memory area, and does not have to decode more than one LSI. Specify an LSI No. by using the PL0 and PL1 pin to determine the layout of the LSIs, and determine the direction (vertical or horizontal) of the liquid crystal display by using the DIR pin.
PL1 0 0 1 1
PL0 0 1 0 1
LSI No. No. 0 No. 1 No. 2 No. 3
10. NUMBER OF COLUMN OUTPUTS SELECTION
CMODE1 0 0 1 1
CMODE0 0 1 0 1
Number of Column Outputs 208 184 160 144
Valid Pins Y1 to Y208 Y1 to Y184 Y1 to Y160 Y1 to Y144
Remark
Invalid column outputs are fastened to V1 level.
11. DUTY SELECTION
DMODE 0 1
Duty 1/160 1/128 Note
Note Valid row outputs of PD16667 are X1 to X128. Invalid row outputs are undefined.
12
Data Sheet S13780EJ1V0DS00
PD16664
*
Horizontally Long Address DIR = L, DMODE = L * 144-output Mode
Specified by A7 to A0
PD16664
Y1 Specified by A16 to A8 X1 00000 00100 No. 0 09E00 X160 X1 09F00 0A000 0A100 09F02 0A002 09F20 0A020 09E22 09F22 0A022 0A122 No. 1 13E00 X160 13F00 Y144 13F02 13F20 13E22 13F22 Y1 13E24 13F24 Y144 09E24 09F24 0A024 0A124 00002 00020 Y144 00022 00122 Y1 00024 00124
PD16664
Y144 00026 00044 00046 00146 No. 2 09E46 09F26 0A026 09F44 0A044 09F46 0A046 0A146 No. 3 13E46 13F26 13F44 13F46 Y1
PD16667
PD16667
PD16664
PD16664
* 160-output Mode
Specified by A7 to A0
PD16664
Y1 Specified by A16 to A8 X1 00000 00100 No. 0 09E00 X160 X1 09F00 0A000 0A100 09F02 0A002 09F24 0A024 09E26 09F26 0A026 0A126 No. 1 13E00 X160 13F00 Y160 13F02 13F24 13E26 13F26 Y1 13E28 13F28 Y160 09E28 09F28 0A028 0A128 00002 00024 Y160 00026 00126 Y1 00028 00128
PD16664
Y160 0002A 0004C 0004E 0014E No. 2 09E4E 09F2A 0A02A 09F4C 0A04C 09F4E 0A04E 0A14E No. 3 13E4E 13F2A 13F4C 13F4E Y1
PD16667
PD16667
PD16664
PD16664
Data Sheet S13780EJ1V0DS00
13
PD16664
* 184-output Mode
Specified by A7 to A0
PD16664 PD16664
Y1 Specified by A16 to A8
PD16667
Y184 00002 0002A 0002C 0012C No. 0
Y1 0002E 0012E No. 2 00030 00058
Y184 0005A 0015A
X1
00000 00100
09E00 X160 X1
PD16667
09E2C 09F02 0A002 09F2A 0A02A 09F2C 0A02C 0A12C No. 1
09E2E 09F2E 0A02E 0A12E No. 3 09F30 0A030 09F58 0A058
09E5A 09F5A 0A05A 0A15A
09F00 0A000 0A100
13E00 X160 13F00 Y184
PD16664
13E2C 13F02 13F2A 13F2C Y1
13E2E 13F2E Y184
PD16664
13E5A 13F30 13F58 13F5A Y1
* 208-output Mode
Specified by A7 to A0
PD16664
Y1 Specified by A16 to A8 X1 00000 00100 00002 00030 Y208 00032 00132 No. 0 09E00 X160 X1 09F00 0A000 0A100 09F02 0A002 09F30 0A030 09E32 09F32 0A032 0A132 No. 1 13E00 X160 13F00 Y208 13F02 13F30 13E32 13F32 Y1 13E34 13F34 Y208 09E34 09F34 0A034 0A134 Y1 00034 00134
PD16664
Y208 00036 00064 00066 00166 No. 2 09E66 09F36 0A036 09F64 0A064 09F66 0A066 0A166 No. 3 13E66 13F36 13F64 13F66 Y1
PD16667
PD16667
PD16664
PD16664
14
Data Sheet S13780EJ1V0DS00
*
Specified by A7 to A0
PD16664 PD16664
Y144 00044 00026 00124 00122 00100 00024 00022 00020 00002 00000 X160 Y1 Y144 Y1 00046 00146
* 144-output Mode
Specified by A16 to A8
Vertically Long Address DIR = H, DMODE = L
PD16667
No. 2 No. 0
09E46 09E24 09E22 09F26 09F24 09F22 09F20 0A026 0A024 0A022 0A020 0A124 0A122 09F46 09F44 0A046 0A044 0A146
09E00 09F02 09F00 0A002 0A000 0A100 X1 X160
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
13E46 13F46 13F44 Y144 13F26
13E24 13E22 13F24 Y1 13F22 13F20 Y144
13E00 13F02 13F00 Y1 X1
PD16664
PD16664
PD16664
15
* 160-output Mode
16
Specified by A7 to A0
PD16664 PD16664
Y1 0004E 0004C 0002A 00128 00100 00126 00028 00026 00024 0014E 00002 00000 X160
Y160 Y160
Y1
Specified by A16 to A8
PD16667
No. 2 No. 0
09E4E 09F4E 09F4C 0A04E 0A04C 0A14E 09F2A 09F28 09F26 09F24 0A02A 0A028 0A026 0A024 0A128 0A126
09E28 09E26
09E00 09F02 09F00 0A002 0A000 0A100 X1 X160
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
13E4E 13F4E 13F4C Y160
PD16664
13E28 13E26 13F2A 13F28 Y1 13F26 13F24 Y160
PD16664
13E00 13F02 13F00 Y1 X1
PD16664
Specified by A7 to A0
PD16664 PD16664
Y184 Y184 00002 00000 00100 X160 00030 0012E 0012C 0002E 0002C 0002A Y1 Y1 0005A 00058 0015A
* 184-output Mode
Specified by A16 to A8
PD16667
No. 2 No. 0
09E5A 09F5A 09F58 0A05A 0A058 0A15A
09E2E 09E2C 09F30 09F2E 09F2C 09F2A 0A030 0A02E 0A02C 0A02A 0A12E 0A12C
09E00 09F02 09F00 0A002 0A000 0A100 X1 X160
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
13E5A 13F5A 13F58 Y184 13F30
13E2E 13E2C 13F2E 13F2C 13F2A Y1 Y184
13E00 13F02 13F00 Y1 X1
PD16664
PD16664
PD16664
17
* 208-output Mode
18
Specified by A7 to A0
PD16664 PD16664
Y1 00066 00064 00036 00134 00100 00132 00034 00032 00030 00166 00002 00000 X160
Y208 Y208
Y1
Specified by A16 to A8
PD16667
No. 2 No. 0
09E66 09F66 09F64 0A066 0A064 0A166 09F36 09F34 09F32 09F30 0A036 0A034 0A032 0A030 0A134 0A132
09E34 09E32
09E00 09F02 09F00 0A002 0A000 0A100 X1 X160
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
13E66 13F66 13F64 Y208
PD16664
13E34 13E32 13F36 13F34 Y1 13F32 13F30 Y208
PD16664
13E00 13F02 13F00 Y1 X1
PD16664
PD16664
*
Horizontally Long Address DIR = L, DMODE = H * 144-output Mode
Specified by A7 to A0
PD16664
Y1 Specified by A16 to A8 X1 00000 00100 No. 0 07E00 X128 X1 07F00 08000 08100 07F02 08002 07F20 08020 07E22 07F22 08022 08122 No. 1 0FE00 X128 0FF00 Y144 0FF02 0FF20 0FE22 0FF22 Y1 0FE24 0FF24 Y144 07E24 07F24 08024 08124 00002 00020 Y144 00022 00122 Y1 00024 00124
PD16664
Y144 00026 00044 00046 00146 No. 2 07E46 07F26 08026 07F44 08044 07F46 08046 08146 No. 3 0FE46 0FF26 0FF44 0FF46 Y1
PD16667
PD16667
PD16664
PD16664
* 160-output Mode
Specified by A7 to A0
PD16664 PD16664
Y1 Specified by A16 to A8
PD16667
Y160 00002 00024 00026 00126 No. 0
Y1 00028 00128 No. 2 0002A 0004C
Y160 0004E 0014E
X1
00000 00100
07E00 X128 X1
PD16667
07E26 07F02 08002 07F24 08024 07F26 08026 08126 No. 1
07E28 07F28 08028 08128 No. 3 07F2A 0802A 07F4C 0804C
07E4E 07F4E 0804E 0814E
07F00 08000 08100
0FE00 X128 0FF00 Y160
PD16664
0FE26 0FF02 0FF24 0FF26 Y1
0FE28 0FF28 Y160
PD16664
0FE4E 0FF2A 0FF4C 0FF4E Y1
Data Sheet S13780EJ1V0DS00
19
PD16664
* 184-output Mode
Specified by A7 to A0
PD16664 PD16664
Y1 Specified by A16 to A18
PD16667
Y184 00002 0002A 0002C 0012C No. 0
Y1 0002E 0012E No. 2 00030 00058
Y184 0005A 0015A
X1
00000 00100
07E00 X128 X1
PD16667
07E2C 07F02 08002 07F2A 0802A 07F2C 0802C 0812C No. 1
07E2E 07F2E 0802E 0812E No. 3 07F30 08030 07F58 08058
07E5A 07F5A 0805A 0815A
07F00 08000 08100
0FE00 X128 0FF00 Y184
PD16664
0FE2C 0FE2E 0FF02 0FF2A 0FF2C Y1 0FF2E Y184
PD16664
0FE5A 0FF30 0FF58 0FF5A Y1
* 208-output Mode
Specified by A7 to A0
PD16664
Y1 Specified by A16 to A8 X1 00000 00100 00002 00030 Y208 00032 00132 No. 0 07E00 X128 X1 07F00 08000 08100 07F02 08002 07F30 08030 07E32 07F32 08032 08132 No. 1 0FE00 X128 0FF00 Y208 0FF02 0FF30 0FE32 0FF32 Y1 0FE34 0FF34 Y208 07E34 07F34 08034 08134 Y1 00034 00134
PD16664
Y208 00036 00064 00066 00166 No. 2 07E66 07F36 08036 07F64 08064 07F66 08066 08166 No. 3 0FE66 0FF36 0FF64 0FF66 Y1
PD16667
PD16667
PD16664
PD16664
20
Data Sheet S13780EJ1V0DS00
*
Specified by A7 to A0
PD16664 PD16664
Y144 00044 00026 00124 00100 00122 00024 00022 00020 00002 00000 X128 Y1 Y144 Y1 00046 00146
* 144-output Mode
Specified by A16 to A8
Vertically Long Address DIR = H, DMODE = H
PD16667
No. 2 No. 0
07E46 07F46 07F44 08046 08026 08020 08124 08122 08024 08022 08146 08044 07F26 07F24 07F22 07F20
07E24 07E22
07E00 07F02 07F00 08002 08000 08100 X1 X128
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
0FE46 0FF46 0FF44 Y144 0FF26
0FE24 0FE22 0FF24 0FF22 0FF20 Y1 Y144
0FE00 0FF02 0FF00 Y1 X1
PD16664
PD16664
PD16664
21
* 160-output Mode
22
Specified by A7 to A0
PD16664 PD16664
Y1 0004E 0004C 0002A 00128 00100 00126 00028 00026 00024 0014E 00002 00000 X128
Y160 Y160
Y1
Specified by A16 to A8
PD16667
No. 2 No. 0
07E4E 07F4E 07F4C 0804E 0804C 0802A 08028 0814E 08026 07F2A 07F28 07F26 07F24 08024
07E28 07E26
07E00 07F02 07F00 08002 08000 08100 X1 X128
Data Sheet S13780EJ1V0DS00
08128 08126
PD16667
No. 3
No. 1
0FE4E 0FF4E 0FF4C Y160
PD16664
0FE28 0FE26 0FF2A 0FF28 0FF26 0FF24 Y1 Y160
PD16664
0FE00 0FF02 0FF00 Y1 X1
PD16664
Specified by A7 to A0
PD16664 PD16664
* 184-output Mode
Y1 0005A 00058 00030 0012E 0012C 00100 0002E 0002C 0002A 0015A 00002 00000 X128
Y184 Y184
Y1
Specified by A16 to A8
PD16667
No. 2 No. 0
07E5A 07F5A 07F58 0805A 08030 0815A 08058 07F30 07F2E 07F2C 07F2A 0802E 0802C 0802A 0812E 0812C
07E2E 07E2C
07E00 07F02 07F00 08002 08000 08100 X1 X128
Data Sheet S13780EJ1V0DS00
PD16667
No. 3
No. 1
0FE5A 0FF5A 0FF58 Y184
PD16664
0FE2E 0FE2C 0FF30 0FF2E 0FF2C 0FF2A Y1 Y184
PD16664
0FE00 0FF02 0FF00 Y1 X1
PD16664
23
* 208-output Mode
24
Specified by A7 to A0
PD16664 PD16664
Y1 00066 00064 00036 00134 00100 00132 00034 00032 00030 00166 00002 00000 X128
Y208 Y208
Y1
Specified by A16 to A8
PD16667
No. 2 No. 0
07E66 07F66 07F64 08066 08036 08034 08166 08064 08032 07F36 07F34 07F32 07F30 08030
07E34 07E32
07E00 07F02 07F00 08002 08000 08100 X1 X128
Data Sheet S13780EJ1V0DS00
08134 08132
PD16667
No. 3
No. 1
0FE66 0FF66 0FF64 Y208
PD16664
0FE34 0FE32 0FF36 0FF34 0FF32 0FF30 Y1 Y208
PD16664
0FE00 0FF02 0FF00 Y1 X1
PD16664
PD16664
12. CPU INTERFACE
12.1 Function of RDY(ready) Pin The internal RAM is a single-port RAM. The CPU is kept waiting so that access from the CPU does not conflict with reading by the driver. (1) Timing
A0 to A16,/UBE
/CS
/OE,/WE Hi-Z RDY Wait Ready Wait Hi-Z
(2) Connection of RDY pin The RDY pin uses a three-state buffer. The RDY pin should be connected to an external pull-up resistor. If more than one LSI are used, the RDY pins of each LSI are wired together.
VCC2 CPU Ready input
Pull-up resistor RDY Column driver
RDY
Column driver
Data Sheet S13780EJ1V0DS00
25
PD16664
12.2 Access Timing
(1) Display data read timing
A16 to A0
/UBE
/CS
/OE Hi-Z RDY Hi-Z D15 to D0 Dout Hi-Z Hi-Z
(2) Display data write timing
A16 to A0
/UBE
/CS
/WE Hi-Z RDY Hi-Z
D15 to D0
Din
(3) Gray level palette data write timing
A16 to A0
/UBE /CS
/WE Hi-Z RDY
D15 to D0
Din
26
Data Sheet S13780EJ1V0DS00
PD16664
13. INITIALIZATIONAL FUNCTION
The PD16664 has two types of initialization functions. 13.1 Initialization by /RESET /RESET is the pin that is used to forcibly initialize the internal status of the IC from outside the IC. In the case of /RESET = L, the internal status of IC is as follows: * Oscillator stopped. * Liquid crystal timing generation circuit initialized. * Internal timing generation circuit initialized. * Self-diagnostic circuit initialized. At power-on, be sure to perform initialization using /RESET.
13.2 Initialization by /REFRH /REFRH is the pin that is used when the internal self-diagnostic circuit initializes the internal status of IC in cases when the timing of the column drivers deviate due to external noise, etc. In the case of /REFRH = L, the internal status of IC is as follows: * Oscillator stopped. * Liquid crystal timing generation circuit initialized. * Internal timing generation circuit initialized.
14. DISPLAY-OFF FUNCTION
When /DOFF = L, all column driver outputs Yn become V1 level, and because the /DOUT output becomes L at the same time, the row driver will be /DOFF' = L and all row driver outputs Xn will also be V1 level. Therefore, the display is forcibly turned off without regard to the display data. At power-on, be sure to make /DOFF = L until each power supply is stabilized. Remark /DOFF' is the input pin of the row driver.
Data Sheet S13780EJ1V0DS00
27
PD16664
15. LIQUID CRYSTAL TIMING GENERATION CIRCUIT
If the master mode is set by making MS high, /FRM and STB are generated at timing with a duty factor (1/128,1/160). Driver drive voltage select signals L1 and L2 are generated for a row driver. /FRM is generated two times in 1 frame. When a duty rate is 1/160, STB is generated 81 times in 1/2 frame and 162 times in 1 frame. When a duty rate is 1/128, STB is generated 65 times in 1/2 frame and 130 times in 1 frame. * /FRM and STB Signal Generation
OSC1 PULSE STB 1 2 3 4
DUTY 1/160 STB 81 1 2 3 80 81 1 2 3 80 81 1 2
/FRM Frame DUTY 1/128 STB 65 1 2 3 64 65 1 2 3 64 65 1 2
/FRM Frame
* L1 and L2 Signal Generation
STB L1 L2
1 1 1
2 1 0
3 1 1
4 1 0
*** *** ***
1 1 0
2 1 1
3 1 0
4 1 1
*** *** ***
1 0 0
2 0 1
3 0 0
4 0 1
*** *** ***
1 0 1
2 0 0
3 0 1
4 0 0
*** *** ***
28
Data Sheet S13780EJ1V0DS00
PD16664
16. SELF-DIAGNOSIS FUNCTION
This function checks whether the timing of each column driver is different from that of the others due to external noise. A slave chip compares internally generated L1 and L2 with L1 and L2 of the master chip. If a discrepancy is found, a refresh signal is transmitted to all column drivers. On reception of the refresh signal, internal reset is effected, and timing is initialized. At this time, the display is turned OFF while /REFRH = L for 4 frame cycles. Discrepancy between L1 and L2 is monitored at the rising edge of /FRM once in 1/2 frame.
L1(master) Discrepancy L2(master) L1(slave) L2 (slave) Discrepancy
/REFRH Initialization Initialization
Block Configuration (slave side)
/RESET
Internal reset
/REFRH Self-diagnosis circuit
L1 L2
Internal L1 signal Internal L2 signal
Data Sheet S13780EJ1V0DS00
29
PD16664
17. SYSTEM CONFIGURATION EXAMPLE
Here is an example using a liquid crystal panel of 416 x 320 pixels, horizontally long by using four PD16664s and two row drivers. * The LSI No. of each column driver is set by the PL0 and PL1 pins. * The DIR pin of each column driver is set to low. * The CMODE0, CMODE1 and DMODE pins of each column driver are set to low. * One of the column drivers is set as a master and the others are set as slaves. The master column driver supplies signals to the slave column drivers and row drivers. * A resistor for oscillation is connected to the OSC1 and OSC2 pins of the master. These pins of the slaves are left open. * All the signals from the system (D0 to D15, A0 to A16, /CS, /OE, /WE, /UBE, RDY, /RESET, and /DOFF) are connected in parallel with the column drivers. A pull-up resistor is connected to the RDY pin. * The TEST pin is used to test the LSI and is open or connected to GND when the system is constructed.
VCC2
PULSE STB /FRM /DOUT,/DOFF' L1 L2 /REFRH Y1
Row driver
RDY /DOFF /RESET D0 to D15 A0 to A16 Control (/CS, /OE, /WE, /UBE)
OSC1
Master No. 0
OSC2
Slave No. 2 Y1 Y208
Y208
Scan direction
160
160
Y208 Slave No. 1
Y1
Scan direction
Row driver
Y208 Slave No. 3
Y1
30
Data Sheet S13780EJ1V0DS00
PD16664
18. CHIP SET POWER-UP SEQUENCE
It is recommended to apply power in the following sequence: VCC2 VCC1 input VDD, VEE V1, V2 Be sure to apply LCD drive voltages V1, V2 in the end.
ON VCC2 OFF ON 4.5 V
VCC1
OFF
0 s or more
CPU Interface (A0 to A16,/CS,/OE, /WE,/UBE,D0 to D15) /RESET
VCC2 0V VCC2 0V 0.3 VCC2
100 ns or longer 0 s or more
VCC2 0.3 VCC2
/DOFF
0V
0 s or more
VDD Note
OFF OFF
ON
VEE Note
ON
0 s or more
ON
V1
OFF ON
V2
OFF
Note VDD and VEE do not have to be turned ON at the same time. Caution Turn OFF power to the chip set in the sequence reverse to the above.
Data Sheet S13780EJ1V0DS00
31
PD16664
19. EXAMPLE OF CONNECTING OF INTERNAL SCHOTTKY BARRIER DIODE OF MODULE TO REINFORCE POWER SUPPLY PROTECTION
VDDNote
VCC1
V2
V1
V0
VSS
VEENote
Diodes enclosed in a dotted line in the above figure must be connected when V0 is other than 0 V (GND).
Note VDD and VEE are LCD power supply lines of row driver. Remark Use schottky barrier diodes with Vf = 0.5 V or less.
32
Data Sheet S13780EJ1V0DS00
PD16664
20. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings (TA = 25C)
Parameter Supply voltage (1) Supply voltage (2)
Note1 Note2 Note1 Note2 Note3
Symbol VCC1 VCC2 VI/O1 VI/O2 VI/O3 TA Tstg
Ratings -0.5 to +6.5 -0.5 to +4.5 -0.5 to VCC1 + 0.5 -0.5 to VCC2 + 0.5 -0.5 to VCC1 + 0.5 -20 to +70 -40 to +125
Unit V V V V V C C
Input/output voltage (1) Input/output voltage (2) Input/output voltage (3)
Operating ambient temperature Storage temperature
Notes 1. VCC1 signals (/FRM, STB, /DOUT, L1, L2, PULSE) 2. VCC2 signals (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH, CMODE0, CMODE1, DMODE) 3. Liquid crystal power (V0, V1, V2, Y1 to Y208) Caution If the absolute maximum rating of even one of the above parameters is exceeded even momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore, specify the values exceeding which the product may be physically damaged. Be sure to use the product within the range of the absolute maximum ratings.
Recommended Operating Conditions (TA = -20 to +70C, V0 = 0 V)
Parameter Supply voltage (1) Supply voltage (2) Input voltage (1) Input voltage (2) V1 input voltage V2 input voltage External resistor for OSC
Note1 Note2
Symbol VCC1 VCC2 VI1 VI2 V1 V2 ROSC
MIN. 4.5 2.4 0 0 V0 V1 75
TYP. 5.0
MAX. 5.5 3.6 VCC1 VCC2 V2 VCC1 270
Unit V V V V V V k
Notes 1. VCC1 signals (/FRM, STB, L1, L2, PULSE) 2. VCC2 signals (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, OSC1, OSC2, /DOFF, TEST, BMODE, /REFRH, CMODE0, CMODE1, DMODE)
Data Sheet S13780EJ1V0DS00
33
PD16664
DC Characteristics (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70C) {VCC2 = 3.0 to 3.6 V
Parameter High-level input voltage (1), VCC1 Note1 Low-level input voltage (1), VCC1 Note1 High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2 High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2
Note2 Note2 Note3 Note3 Note4 Note4 Note1 Note1,3 Note5 Note5
Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 II1
Conditions
MIN. 0.7 VCC1
TYP.
MAX.
Unit V
0.3 VCC1 0.7 VCC2 0.3 VCC2 0.8 VCC2 0.2 VCC2 IOH = -1 mA IOL = 2 mA IOH = -2 mA IOL = 4 mA IOH = -1 mA IOL = 2 mA Other than TEST pin, V1 = VCC2 or GND VCC2 - 0.4 0.4 10 VCC1 - 0.4 0.4 VCC1 - 0.4 0.4
V V V V V V V V V V V
High-level output voltage (1), VCC1 Low-level output voltage (1), VCC1 High-level output voltage (2), VCC1 Low-level output voltage (2), VCC1 High-level output voltage (3), VCC2 Low-level output voltage (3), VCC2 Input leakage current (1)
A A A A A A
k
Input leakage current (2)
II2
Pull down (TEST pin), V1 = VCC2
10
40
100
* * * *
Display operating current consumption (1) Display operating current consumption (2) Display operating current consumption (3) Display operating current consumption (4) Liquid crystal driver output ON resistance
Note6 Note6 Note6 Note6 Note7
IMAS1 IMAS2 ISLV1 ISLV2 RON
Master, VCC1 Master, VCC2 Slave, VCC1 Slave, VCC2 1
80 200 50 130 2
Notes 1. VCC1 signal (/FRM, STB, L1, L2, PULSE) 2. VCC2 signal (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF, TEST, BMODE, CMODE0, CMODE1, DMODE) 3. /REFRH pin 4. /DOUT pin 5. D0 to D15, RDY, OSC2 pins 6. Frame frequency: 70 Hz, output: no load, not accessed by CPU (D0 to D15, A0 to A16, /UBE = GND, /CS, /OE, /WE = VCC2) 7. Resistance between Y and V pins (any of V0, V1, and V2) when a load current (ION = 100 A) flows through one pin of Y1 to Y208.
34
Data Sheet S13780EJ1V0DS00
PD16664
{ VCC2 = 2.4 to 3.0 V
Parameter High-level input voltage (1), VCC1 Low-level input voltage (1), VCC1
Note1
Symbol VIH1 VIL1 VIH2 VIL2 VIH3 VIL3 VOH1 VOL1 VOH2 VOL2 VOH3 VOL3 II1
Conditions
MIN. 0.7 VCC1
TYP.
MAX.
Unit V
Note1 Note2
0.3 VCC1 0.7 VCC2 0.3 VCC2 0.8 VCC2 0.2 VCC2 IOH = -1 mA IOL = 2 mA IOH = -2 mA IOL = 4 mA IOH = -1 mA IOL = 2 mA Other than TEST pin, V1 = VCC2 or GND VCC2 - 0.4 0.4 10 VCC1 - 0.4 0.4 VCC1 - 0.4 0.4
V V V V V V V V V V V
High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2
Note2 Note3
High-level input voltage (2), VCC2 Low-level input voltage (2), VCC2
Note3 Note4
High-level output voltage (1), VCC1 Low-level output voltage (1), VCC1
Note4 Note1
High-level output voltage (2), VCC1 Low-level output voltage (2), VCC1
Note1,3 Note5
High-level output voltage (3), VCC2
Low-level output voltage (3), VCC2 Note5 Input leakage current (1)
A A A A A A
k
Input leakage current (2)
II2
Pull down (TEST pin), V1 = VCC2
10
40
100
* * * *
Display operating current consumption (1) Display operating current consumption (2) Display operating current consumption (3) Display operating current consumption (4)
Note6 Note6 Note6 Note6
IMAS1 IMAS2 ISLV1 ISLV2
Master, VCC1 Master, VCC2 Slave, VCC1 Slave, VCC2 1.2
100 150 60 100 2.4
Liquid crystal driver output ON resistance Note7 RON
Notes 1. VCC1 signal (/FRM, STB, L1, L2, PULSE) 2. VCC2 signal (MS, DIR, PL0 and PL1, A0 to A16, /CS, /OE, /WE, /UBE, RDY, D0 to D15, /RESET, /DOFF, TEST, BMODE, CMODE0, CMODE1, DMODE) 3. /REFRH pin 4. /DOUT pin 5. D0 to D15, RDY, OSC2 pins 6. Frame frequency: 70 Hz, output: no load, not accessed by CPU (D0 to D15, A0 to A16, /UBE = GND, /CS, /OE, /WE = VCC2) 7. Resistance between Y and V pins (any of V0, V1, and V2) when a load current (ION = 100 A) flows through one pin of Y1 to Y208.
Data Sheet S13780EJ1V0DS00
35
PD16664
AC Characteristics 1 Display Data Transfer Timing (1) Master Mode (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 2.4 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70C, frame frequency: 70 Hz (fOSC = 90.72 kHz at 1/160 duty, 72.8 kHz at 1/128 duty), output load: 100 pF)
Parameter STB clock cycle time Symbol tCYC Conditions 1/160 duty 1/128 duty STB high-level width tCWH 1/160 duty 1/128 duty STB low-level width tCWL 1/160 duty 1/128 duty STB rise time STB fall time STB - /FRM delay time /FRM - STB delay time tR tF tPSF tPFS
tCYC tCWL tF tR tCWH
MIN. 87 108 43 54 43 54
TYP. 8/fOSC 8/fOSC 4/fOSC 4/fOSC 4/fOSC 4/fOSC
MAX.
Unit
s s s s s s
100 100 ns ns
20 20
s s
STB (output) tPSF tPFS tPSF tPFS
0.9 VCC1 0.1 VCC1
0.9 VCC1 /FRM (output) 0.1 VCC1
36
Data Sheet S13780EJ1V0DS00
PD16664
(2) Slave mode (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, VCC2 = 2.4 to 3.6 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70 C)
Parameter STB clock cycle time STB high-level width STB low-level width STB rise time STB fall time /FRM setup time /FRM hold time Symbol tCYC tCWH tCWL tR tF tSFR tHFR
tCYC tCWL tF tR tCWH
Conditions
MIN. 10 4 4
TYP.
MAX.
Unit
s s s
150 150 ns ns
1 1
s s
STB (input) tSFR tHFR tSFR tHFR
0.7 VCC1 0.3 VCC1
0.7 VCC1 /FRM (input) 0.3 VCC1
Data Sheet S13780EJ1V0DS00
37
PD16664
(3) Parameters Common to Master/Slave (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70C) {VCC2 = 3.0 to 3.6 V
Parameter Output delay time (L1, L2) Output delay time (Y1 to Y208) Symbol tDOUT1 tDOUT2 Conditions No output load No output load MIN. TYP. 50 90 MAX. 100 150 Unit ns ns
{VCC2 = 2.4 to 3.0 V
Parameter Output delay time (L1, L2) Output delay time (Y1 to Y208) Symbol tDOUT1 tDOUT2 Conditions No output load No output load MIN. TYP. MAX. 120 180 Unit ns ns
STB (output) tDOUT1
0.9 VCC1 tDOUT1
L1, L2 tDOUT2 0.9 V2
0.9 VCC1 tDOUT2
0.1 V2 Y1 to Y208 0.9 V2 0.1 V2
38
Data Sheet S13780EJ1V0DS00
PD16664
AC Characteristics 2 Drawing Access Timing (Unless otherwise specified, VCC1 = 4.5 to 5.5 V, V0 = 0 V, V1 = 1.4 to 2.0 V, V2 = 2.8 to 4.0 V, TA = -20 to +70C, tr = tf = 5 ns) {VCC2 = 3.0 to 3.6 V
Parameter /OE,/WE recovery time Address setup time Address hold time RDY output delay time RDY float time
Note 1 Note 2 Note 2
Symbol tRY tAS tAH tRYR tRYZ tRYW tRYF1 tRYF2 tACS tHZ tCSOE tOECS tWP1 tWP2 tDW tDH tCSWE tWECS tWRES tRDOE tRDWE
Conditions
MIN. 30 10 20
TYP.
MAX.
Unit ns ns ns
CL = 15 pF
30 30 35 60 650 100 1200 100 40 10 20 50 50 20 20 10 20 100 Note 4 Note 4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - -
Wait status time
Ready status time (without conflict) Ready status time (with conflict) Data access time (read cycle) Data float time (read cycle) /CS - /OE time (read cycle) /OE - /CS time (read cycle)
Note 2
Note 3
Note 1
Write pulse width 1 (write cycle 1) Note 2 Write pulse width 2 (write cycle 2) Data setup time (write cycles 1, 2) Data hold time (write cycles 1, 2) /CS - /WE time (write cycles 1, 2) /WE - /CS time (write cycles 1, 2) Reset pulse width RDY - /OE time RDY - /WE time
Note 2
Notes 1. Load circuit
VCC2 1.8 k
1.0 k
5 pF
Data Sheet S13780EJ1V0DS00
39
PD16664
2. Load circuit
VCC2 1.8 k
1.0 k
60 pF
3. Load circuit
VCC2 1.8 k
1.0 k
100 pF
4. The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended that tRDOE and tRDWE be 1000 ns or less.
40
Data Sheet S13780EJ1V0DS00
PD16664
{VCC2 = 2.4 to 3.0 V
Parameter /OE,/WE recovery time Address setup time Address hold time RDY output delay time RDY float time
Note 1 Note 2 Note 2
Symbol tRY tAS tAH tRYR tRYZ tRYW tRYF1 tRYF2 tACS tHZ tCSOE tOECS tWP1 tWP2 tDW tDH tCSWE tWECS tWRES tRDOE tRDWE
Conditions
MIN. 40 20 30
TYP.
MAX.
Unit ns ns ns
CL = 15 pF
40 40 50 120 1600 120 50 20 30 60 60 30 30 20 30 120 Note 4 Note 4
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns - -
Wait status time
Ready status time (without conflict) Ready status time (with conflict) Data access time (read cycle) Data float time (read cycle) /CS - /OE time (read cycle) /OE - /CS time (read cycle)
Note 2
Note 3
Note 1
Write pulse width 1 (write cycle 1) Note 2 Write pulse width 2 (write cycle 2) Data setup time (write cycles 1, 2) Data hold time (write cycles 1, 2) /CS - /WE time (write cycles 1, 2) /WE - /CS time (write cycles 1, 2) Reset pulse width RDY - /OE time RDY - /WE time
Note 2
Notes 1. Load circuit
VCC2 1.8 k
1.0 k
5 pF
Data Sheet S13780EJ1V0DS00
41
PD16664
2. Load circuit
VCC2 1.8 k
1.0 k
60 pF
3. Load circuit
VCC2 1.8 k
1.0 k
100 pF
4. The display may be affected if the time from the rising of RDY to /OE or /WE is too long. It is recommended that tRDOE and tRDWE be 1000 ns or less.
42
Data Sheet S13780EJ1V0DS00
PD16664
/OE,/WE Recovery Time
tRY 0.7 VCC2 /OE,/WE 0.3 VCC2
Read Cycle
A16 to A0 /UBE tAS tAH 0.7 VCC2 /CS 0.3 VCC2 tCSOE tRDOE tOECS 0.7 VCC2 /OE tRYR RDY Hi-Z tRYF 0.3 VCC2 tRYW tRYZ 0.9 VCC2 0.1 VCC2 tACS 0.1 VCC2 tHZ 0.9 VCC2 0.1 VCC2 0.3 VCC2 0.7 VCC2 0.3 VCC2
D15 to D0
OUT
Data Sheet S13780EJ1V0DS00
43
PD16664
Write Cycle 1 (on writing display data)
0.7 VCC2 0.3 VCC2 tAS tAH 0.7 VCC2 /CS 0.3 VCC2 tCSWE tRDWE tWECS 0.7 VCC2 /WE tRYR RDY Hi-Z tRYF 0.3 VCC2 tRYW tRYZ 0.9 VCC2 0.1 VCC2 tWP1 0.1 VCC2 0.3 VCC2
A16 to A0 /UBE
D15 to D0
IN tDW tDH
0.7 VCC2 0.3 VCC2
Write Cycle 2 (on writing gray level palette)
0.7 VCC2 0.3 VCC2 tAS tAH
A16 to A0 /UBE
/CS
0.3 VCC2 tCSWE tWECS 0.7 VCC2
/WE tWP2 RDY Hi-Z
0.3 VCC2
D15 to D0
IN tDW tDH
0.7 VCC2 0.3 VCC2
44
Data Sheet S13780EJ1V0DS00
PD16664
Reset Pulse Width
/RESET 0.3 VCC2 tWRES
AC Characteristics 3 CR Oscillation {VCC2 = 2.4 to 3.6 V, TA = -20 to +70 C, 1/160 duty
Parameter Oscillation frequency Frame frequency Symbol fOSC - Conditions External resistor: 130 k External resistor: 130 k MIN. 80 61.7 TYP. 95 73.3 MAX. 110 84.9 Unit kHz Hz
{VCC2 = 2.4 to 3.6 V, TA = -20 to +70 C, 1/128 duty
Parameter Symbol fOSC - Conditions External resistor: 160 k External resistor: 160 k MIN. 64 61.5 TYP. 76 73.1 MAX. 88 84.6 Unit kHz Hz
* *
Oscillation frequency Frame frequency
Data Sheet S13780EJ1V0DS00
45
PD16664
21. RELATION BETWEEN OSCILLATION FREQUENCY, FRAME FREQUENCY, AND STB FREQUENCY
The relation between the oscillation frequency, frame frequency, and STB frequency is as follows: 1/160 duty
1 x Oscillation frequency 162 x 2 x 4
Frame frequency =
STB frequency =
1 x Oscillation frequency 2x 4
1/128 duty
1 x Oscillation frequency 130 x 2 x 4
Frame frequency =
STB frequency =
1 x Oscillation frequency 2x 4
46
Data Sheet S13780EJ1V0DS00
PD16664
22. PACKAGE DRAWINGS
Standard TCP Package Drawing (PD16664N-001) (1/3)
Material Polyimide UPILEX-S t = 75 m Adhesive Epoxy t = 12 m Copper Electrolysis Cu t = 18 m Plating Sn t = 0.15 m min Solder Resist Epoxy t = 25 m This products is single side Flex type. This figure is shown by Copper side over Polymide. All tolerances unless otherwise specified 0.05 mm. Corner radius is 0.30 mm MAX. 13 Sprocket holes (61.75 mm) for 1 Pattern.
Data Sheet S13780EJ1V0DS00
47
PD16664
Standard TCP Package Drawing (PD16664N-001) (2/3) EIAJ test pad details
from P.C.
from P.C.
Alignment details
from P.C.
TCP tape winding direction
Output lead
from P.C.
Wind-up direction The Cu pattern side is the underside of the tape
Tape pull-up direction
48
Data Sheet S13780EJ1V0DS00
PD16664
Standard TCP Package Drawing (PD16664N-001) (3/3) Pin configuration
No.1 DUMMY V0 No.2 V1 No.3 V2 No.4 VCC1 No.5 GND No.6 VCC2 No.7 GND No.8 A0 No.9 A1 No.10 A2 No.11 A3 No.12 A4 No.13 A5 No.14 A6 No.15 A7 No.16 A8 No.17 A9 No.18 A10 No.19 A11 No.20 A12 No.21 A13 No.22 A14 No.23 A15 No.24 A16 No.25 D0 No.26 D1 No.27 D2 No.28 D3 No.29 D4 No.30 D5 No.31 D6 No.32 D7 No.33 D8 No.34 D9 No.35 D10 No.36 D11 No.37 D12 No.38 D13 No.39 D14 No.40 D15 No.41 VCC2 No.42 OSC1 No.43 OSC2 No.44 GND No.45 DIR No.46 PL0 No.47 PL1 No.48 No.49 /REFRH No.50 /RESET /UBE No.51 /CS No.52 /OE No.53 /WE No.54 RDY No.55 /DOFF No.56 TEST No.57 No.58 BMODE No.59 CMODE0 No.60 CMODE1 No.61 DMODE MS No.62 VCC2 No.63 GND No.64 No.65 PULSE /FRM No.66 STB No.67 No.68 /DOUT L2 No.69 L1 No.70 VCC1 No.71 GND No.72 V2 No.73 V1 No.74 V0 No.75 No.76 DUMMY
DUMMY DUMMY Y208 Y207 Y206 Y205 Y204 Y203 Y202 Y201 Y200 Y199
No.1 No.2 No.3 No.4 No.5 No.6 No.7 No.8 No.9 No.10 No.11 No.12
Y10 Y9 Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 DUMMY DUMMY
No.201 No.202 No.203 No.204 No.205 No.206 No.207 No.208 No.209 No.210 No.211 No.212
Data Sheet S13780EJ1V0DS00
49
PD16664
[MEMO]
50
Data Sheet S13780EJ1V0DS00
PD16664
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. 2 HANDLING OF UNUSED INPUT PINS FOR CMOS Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 STATUS BEFORE INITIALIZATION OF MOS DEVICES Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
Data Sheet S13780EJ1V0DS00
51
PD16664
Reference Documents NEC Semiconductor Device Reliability/Quality Control System (C10983E) Quality Grades to NEC's Semiconductor Devices (C11531E)
* The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. * No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. * NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. * Descriptions of circuits, software, and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software, and information in the design of the customer's equipment shall be done under the full responsibility of the customer. NEC Corporation assumes no responsibility for any losses incurred by the customer or third parties arising from the use of these circuits, software, and information. * While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. * NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance.
M7 98. 8

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